One of the greatest challenges of growing SiC epitaxial films by high temperature chemical vapor deposition (CVD) is to restrict the gas phase nucleation or cluster formation or aerosol formation of silicon during growth. These particles adversely influence the growth by reducing the growth rate due to precursor losses and degrade the crystal quality since the Si droplets are carried to the crystal growth surface by the H2 carrier gas. Moreover, liquid aerosol particles are viscous and adhere to the gas delivery system (parasitic deposition) and causes severe degradation of the reactor parts during epitaxial growth. These depositions (parasitic deposition) are generally flaky, loosely bound, and can be carried to the growth surface during the growth resulting in degradation of crystal quality, introducing defects in the growing epitaxial film. The aforesaid condition is specifically severe at higher precursor gas flow rates required to achieve high film growth rates. Long duration epitaxial growth to achieve thick epitaxial films is also very inconvenient using conventional Si precursors due to excessive Si cluster formation and parasitic deposition in the reactor.
Typical growth rates using silane as the Si precursor in SiC CVD are 1 μm/hour-10 μm/hour. Supersaturation and Si cluster formation prohibit increased rate of mass transport by higher flow rate of the silane precursor. At increased flow, formed Si clusters degrade crystal quality as noted earlier. Cluster formation of particles (Si) is the leading cause of yield loss in semiconductor processing and the critical particle size should be reduced as the microelectronic size decreases.
The major drawback associated with the silane chemistry in achieving high growth rates is the relatively weak bond strength of the Si—H (318 kJ/mol) bond in SiH4 causing it to dissociate easily (and very early in the gas delivery system) into elemental Si. In high temperature silicon carbide (SiC) chemical vapor deposition (CVD) using silane, the dissociated elemental silicon with free dangling bonds can easily form the Si—Si bond during their collisions and initiate liquid Si droplet or aerosol formation. The condition for Si droplet or aerosol formation is particularly severe in SiC CVD (compared to Si CVD), using silane gas, where high temperature (typically 1550° C.) is essential to achieve SiC homoepitaxial growth.
To prevent Si droplet formation in SiC CVD, chlorinated precursors (for e.g., SiCl4, SiHCl3, SiH2Cl2) are typically used. The silicon-chlorine bond is higher in chlorosilanes (for e.g., dichlorosilane, DCS, SiH2Cl2) compared to silicon-hydrogen bond in silane (381 kJ/mol versus 318 kJ/mol). The silicon-chlorine bond strength in dichlorosilane is strong enough to prevent silicon droplet formation in low temperature Si CVD growth (typically 1000° C.) where the stronger Si—Cl bond restricts elemental Si formation. However, in higher temperature SiC growth (typically 1500° C. or above), dichlorosilane (SiH2Cl2) can also generate silicon droplets with increased parasitic deposition at higher gas flow rates leading to degraded epilayer surface morphology. Parasitic deposition in the reactor, using DCS, is discussed later in comparison to conventional silane gas (see also, FIGS. 2-3).
Silicon tetrafluoride gas has been used for polycrystalline silicon carbide films deposited by low power radio frequency plasma decomposition of SiF4. Silicon tetrafluoride gas has also been used for growing μ-crystalline 3C growth using low temperature hotwire CVD using Si substrate. However, homoepitaxial growth on SiC substrates by hot wall, high temperature CVD has not been reported for high quality, thick film growth. Moreover, it is believed in the art that SiF4 is not a suitable gas for SiC epitaxial growth due to its “too strong” Si—F bond (565 kJ/mol).
A continuing need exists for higher growth rates that can result in a high quality, thick homoepitaxial SiC epilayer, particularly those methods that can inhibit and/or prevent formation of silicon droplets and/or parasitic growth during CVD.
Additionally, in SiC bipolar devices, basal plane dislocations (BPDs) in the epitaxial regions generate Shockley stacking faults (SFs) under device current stress, and increase the forward voltage drift. In SiC epitaxial growth, the BPDs mainly come from the substrate. About 70-90% of BPDs on the substrate are converted to benign threading edge dislocations (TEDs), but 10-30% of BPDs propagate from the substrate into the epitaxial layer causing a BPD density of 102-103 cm−2 in the epilayer. For sufficient yield (up to 90%) of bipolar devices, without forward voltage drift reliability problems, it is essential that the density of these performance-limiting defects in the epitaxial layer be less than 10 cm−2.
It has also been reported that in SiC epitaxial growth, the conversion of BPDs occurs during the growth of ˜20 μm thick epilayer, which indicates that there may be BPDs buried within the 20 μm epilayer even though no BPDs are observed on the top surface of over 20 μm thick epilayer. These buried BPDs may still be converted to Shockley SFs under current stress, and these SFs will extend into the drift layers and degrade the device performance. The deeper the depth from the epilayer surface that the BPDs are buried, the higher the current density that is required to convert them to SFs.
In order to reduce the BPD density in the epilayer (i.e., enhance BPD to TED conversion rate), one of the effective methods is etching the substrate in a molten pure KOH or regular KOH—NaOH eutectic solution prior to the epitaxial growth. Both etching methods need to generate etch pits at the points of BPDs intersecting the substrate surface. BPD etch pits >10 μm in diameter are required to achieve BPD density <10 cm−2 on the epilayer surface. In addition, due to the aggressive etching methods by molten KOH or regular KOH—NaOH eutectic, surface damage cannot be avoided even in the defect free regions of the substrate. All of the etch pits (including BPDs, TEDs and threading screw dislocations (TSDs)) and the surface damage on the substrate will be replicated to the epilayer surface. Post-polishing process is mandatory in order to obtain a smooth surface for device fabrication on the resulting epilayer, which reduces the practicability of the substrate etching method.
Therefore, conversion of BPD to TED near the epilayer/substrate interface without degrading the surface morphology is an important need for the reliability of SiC devices.